CMPS430 Final
Terms
- CPU time =
-
Instruction_Count x CPI x clock_cycle
or
(Instruction_Count x CPI) / clock_rate
- 5 Steps of the Load Instruction
-
IF - Instruction Fetch
ID - Instruction Decode
Exe - Execute
Mem - Memory Read/Write
WB - Write Back
-
Instruction j tries to read a source operand before instruction i writes it.
Hazard type:
- RAW
-
Instruction J tries to write an operand before instruction i writes it.
Hazard type:
- WAW
-
Instruction j tries to write an operand before instruction i reads it.
Hazard type:
- WAR
-
Memory Hierarchy:
-
Processor / Reg File
L1 Cache
L2 Cache
Main Memory
Secondary Memory
- Temporal Locality:
-
Locality in Time
Keep most recently accessed data items closer to the processor.
-
Spatial Locality:
-
Locality in space
Move blocks consisting of contiguous words to thee upper levels.
- What are the 4 questions for memory Hierarchy?
-
1: Where can a block be placed in the upper level? (Block placement)
2: How is a block found if it is in the upper level? (Block identification)
3: Which block should be replaced on a miss? (Block replacement)
4: What happens on a wri
-
How do we improve cache performance?
-
- Reduce the time to hit in the cache
- smaller cache
- direct mapped cache
- smaller blocks
- for writes
- no write allocate - no "hit" on cache, just write to write buffer
- write allocate - to
- Daisy Chain Method
-
Uses a three fix priority method where Device1 is highest priority to Device 3/N lowest priority. Example, like Round Robin |D1|D2|D3|...|DN|
Whenever Device 1's request completes its function, it releases the signal line to Device2, th
- Why is there a need for Bus Arbitration?
-
- Multiple devices may need to use the bus at the same time so the must have a way to arbitrate multiple requests.
- Bus Arbitration schemes usually try to balance:
- Bus priority - highest priority device should be serviced first.
- What are 3 types of Buses?
-
- Processor - memory bus
- short and high speed
- matched to the memory system to maximize the memory-processor bandwidth
- optimized for cache block transfers
- I/O bus (industry standard eg. SCSI, USB, Firew
- Processor - memory bus
- Asynchronous Bus Handshaking Protocol:
-
- I/O Device signals a request by
- raising ReadReq and
- putting the (memory) address on the data lines
- Memory sees
- I/O Device signals a request by