CMPS430 final v2
Terms
undefined, object
copy deck
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4 bit binary adder is?
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4 full adders chained together, carry_out into carry_in
- 4 Questions for memory hierarchy?
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Where can a block be placed in the upper level?
How is a block found if it is in the upper level?
Which block should be replaced on a miss?
What happens on a write? -
Asynchronous Bus
- Not clocked, requires a handshaking protocol and control lines. Accommodates all speed devices, slower.
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Asynchronous Handshaking Protocol
- Used in absence of a clock to coordinate communication between devices. (Read mem to I/O)
- cluster
- multiple computers (each with their own address space) connected over a LAN functioning as a single system.
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Daisy Chain Arbitration
- Simple. Low priority devices may be locked out. Big brother controls the video game.
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Decoder is?
- n-to-m (eg 3 to 8) line, takes binary input (eg 110), maps to one of 8 outputs, representing decimal value
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Direct Memory Access
- I/O controller has the ability to transfer data directly to/from the memory without involving the CPU.
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Encoder is?
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m-to-n (eg 8 to 3) line, takes decimal input (eg 6), maps to one of 3 outputs, representing binary value (110)
- Example of a SIMD machine?
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Illiac IV
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Five steps of the load instruction?
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IF, ID, EXE, MEM, WB
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Full-adder is?
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2 inputs, 1 sum, 1 carry_out, 1 carry_in
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Half-adder is?
- 2 inputs, 1 sum, 1 carry_out
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How is a block found if it is in the upper level?
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Direct map - by index
Set Assoc. - index the set, compare set's tags
Fully Assoc. - compare all block tags
- How to improve cache performance?
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Reduce time to hit - smaller, direct mapped, smaller blocks.
Reduce miss rate - bigger cache, larger blocks, more flexible placement (higher associativity)
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Memory-mapped I/O
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Portions of High order mem. address assigned to each I/O device. R/W to addr. interpreted as command to I/O device. Can only be done by OS.
- MIMD
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multiple instruction, multiple data streams
multiprocessors
- MISD
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multiple instruction, single data
no such thing
- Moores Law?
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# of transistors integrated on a die doubles every 18-24 months
- multiprocessor
- multiple processors with a single shared address space
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N-type MOS...
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positive voltage = closed switch/circuit
negative voltage = open switch/circuit - P-type MOS
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positive voltage = open switch/circuit
negative voltage = closed switch/circuit - RAID 0
- No Redundancy, Striping. Spreads blocks over multiple disks. Increased performance.
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RAID 1
- Redundancy via mirroring. Expensive, 2x the disks.
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RAID 2
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Redundancy via Error Correction Codes, no longer used.
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RAID 3
- Bit-interleaved parity. Byte level striping, with a dedicated parity disk.
- RAID 4
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Block interleaved parity. Block level striping with a dedicated parity disk.
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RAID 5
- Distributed block-interleaved parity. Block level striping with parity data distributed across all member disks.
- RAID stands for
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Redundant Array of Inexpensive Disks
- RAW
- Instruction j tries to read a source operand before instruction i writes it.
- SIMD
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single instruction, multiple data stream
1 unit broadcasting operations to multiple datapaths
- Single cycle implementation (s.l.o.w)
- Describes which instruction types do/don't do stages of an instruction. R-Type: no MEM, LW: all, SW: no WB, Branch: no MEM or WB, Jump: only IF
- SISD
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single instructio, single data stream
uniprocessor
- Synchronous Bus
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clock in the control lines, has a fixed protocol for communication relative to the clock.
Fast. All must have same clock Rate.
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This is a measure of service accomplishment,
MTTF/(MTTF + MTTR)
- Availability
- This is measured by mean time to repair (MTTR):
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Service interruption
- This is measured by the mean time to failure (MTTF):
- Reliability
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Typical I/O System
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Processor - Cache - Memory I/O Bus - Main Memory
Processor - Interrupt - Mem I/O Bus - IO Controller - (Disk,Graphics, Network) - Typical Memory Hierarchy
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Processor
L1
L2
Main Memory
Secondary Memory
- WAR
- instruction j tries to read a source operand before instruction i writes it
- WAW
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Instruction j tries to write to an operand before instruction I writes it.
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What are the 3 hazards of pipelining?
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Structural
Data Hazard
Control Hazards
- What are the 3 types of busses?
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Processor-memory bus
I/O Bus
Backplane Bus (bus between IO and CPU/Mem bus) -
What happens on a write?
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Write through - writes both to block in cache and block in memory
Write back - data only written to block in chache. Written to main memory only when it is replaced.
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What is write-through?
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When the ALU writes to cache, also writes to memory.
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Where can a block be placed in the upper level?
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Direct map - memory location modulus # of blocks
Set Assoc. - set of blocks it must be mapped to
Fully Assoc. - can go anywhere... 1 set - Which block should be replaced on a miss?
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Direct map - only on choice
Set or Fully assoc. - random, or LRU (least recently used)